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Home › Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices

Double-row address decoding and selection circuitry for an electrically erasable and programmable non-volatile memory device with redundancy, particularly for flash EEPROM devices

US Patent 5581509 · Granted Dec 3, 1996

Estimated economic value: $15,022,000 ⓘ

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