Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

US Patent 5581101 · Granted Dec 3, 1996

Estimated economic value: $20,817,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Darlington pair bipolar junction transistor sensor2024
Direct growth of lateral III-V bipolar transistor on silicon substrate2024
Series connected stacked vertical transistors for high voltage applications2024
Vertical bipolar junction transistor with all-around extrinsic base and epitaxia2023
Depth map generation device2023
Stacked vertical transport field effect transistor electrically erasable program2023
Nanosheet transistor with body contact2022
Stacked vertical transistor erasable programmable read-only memory and programma2022
III-V lateral bipolar junction transistor on local facetted buried oxide layer2022
III-V lateral bipolar junction transistor on local facetted buried oxide layer2022
Biosensors including surface resonance spectroscopy and semiconductor devices2022
Biosensors including surface resonance spectroscopy and semiconductor devices2022