{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Redundancy circuitry layout for a semiconductor memory device", "item": "https://www.patentleaderboard.com/patent/5559743"}]}
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Home › Redundancy circuitry layout for a semiconductor memory device

Redundancy circuitry layout for a semiconductor memory device

US Patent 5559743 · Granted Sep 24, 1996

Estimated economic value: $12,666,000 ⓘ

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