Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Low temperature process for annealing shallow implanted N+/P junctions

Low temperature process for annealing shallow implanted N+/P junctions

US Patent 4522657 · Granted Jun 11, 1985

Estimated economic value: $3,234,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nano-scale light intensity concentration control2025
Manufacture of power MOSFETs2025
And manufacture of robust, high-performance devices2025
Manufacture of robust, high-performance devices2025
Manufacture of power devices having increased cross over current2025
Manufacture of power devices having increased cross over current2025
Inversion channel devices on multiple crystal orientations2024
And manufacture of power devices having increased cross over current2024
Designs for silicon carbide MOSFETs2024
And manufacture of self-aligned power devices2024
Inversion channel devices on multiple crystal orientations2024
Manufacture of power devices having increased cross over current2023