Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 4532702 | Method of forming conductive interconnection between vertically spaced levels in VLSI devices | Rathindra N. Ghoshtagore | 1985-08-06 |
| 4522657 | Low temperature process for annealing shallow implanted N+/P junctions | Ajeet Rohatgi, Prosenjit Rai-Choudhury, Ranbir Singh, Stephen J. Fonash | 1985-06-11 |
| 4372803 | Method for etch thinning silicon devices | — | 1983-02-08 |