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Home › Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes

Shift register latch circuit means contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques and utilized at least in part for check and test purposes

US Patent 4476431 · Granted Oct 9, 1984

Estimated economic value: $20,988,000 ⓘ

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