Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation

Process for making CMOS field-effect transistors with self-aligned guard rings utilizing special masking and ion implantation

US Patent 4468852 · Granted Sep 4, 1984

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Seebeck/Peltier thermoelectric conversion element with parallel nanowires of con2016
Seebeck/peltier thermoelectric conversion device having phonon confinement layer2016
Seebeck/peltier thermoelectric conversion device employing treated films of semi2015
Method for realizing a nanometric circuit architecture between standard electron2013
Nanometric device with a hosting structure of nanometric elements2011
Method for realizing an electric linkage in a semiconductor electronic device be2011
Electric linkage in a semiconductor electronic device between a nanometric circu2011
Method for realizing a multispacer structure, use of said structure as a mold an2011
Nanometric structure and corresponding manufacturing method2010
Method and device for demultiplexing a crossbar non-volatile memory2010
Method for realizing an electric linkage in a semiconductor electronic device be2009
Method and device for demultiplexing a crossbar non-volatile memory2009