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Home › Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection

Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection

US Patent 4441075 · Granted Apr 3, 1984

Estimated economic value: $11,562,000 ⓘ

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