Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Top level network and array level network for reconfigurable data processors

Top level network and array level network for reconfigurable data processors

US Patent 12306783 · Granted May 20, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Lossless tiling in convolution networks—tiling configuration between two section2025
Lossless tiling in convolution networks—tiling configuration between two section2025
Lossless tiling in convolution networks—tiling configuration between two section2025
Execution state management2025
Execution state management2025
Integrated circuit that mitigates inductive-induced voltage droop2025
Integrated circuit that mitigates inductive-induced voltage droop2025
Configuration file generation for fracturable data path in a coarse-grained reco2025
Lossless tiling in convolution networks—padding and re-tilling at section bounda2025
Lossless tiling in convolution networks—padding and re-tilling at section bounda2025
Lossless tiling in convolution networks—padding and re-tilling at section bounda2025
Dataflow architecture processor statically reconfigurable to perform n-dimension2025