Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices

Selective and dynamic deployment of error correction code techniques in integrated circuit memory devices

US Patent 12277978 · Granted Apr 15, 2025

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Classification of error rate of data retrieved from memory cells2025
Classification of error rate of data retrieved from memory cells2025
Memory device producing metadata characterizing applied read voltage level with 2025
Memory device producing metadata characterizing applied read voltage level with 2025
Error decoding with soft redundant array of independent NAND (RAIN)2025
Search for an optimized read voltage2025
Search for an optimized read voltage2025
Generating semi-soft bit data during corrective read operations in memory device2025
Generating semi-soft bit data during corrective read operations in memory device2025
Adaptive integrity scan rates in a memory sub-system based on block health metri2025
Memory read calibration based on memory device-originated metrics characterizing2025
Memory read voltage threshold tracking based on memory device-originated metrics2025