Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Combining peripheral component interface express partial store commands along cache line boundaries

Combining peripheral component interface express partial store commands along cache line boundaries

US Patent 12158848 · Granted Dec 3, 2024

Estimated economic value: $48,995,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Input/output (I/O) store protocol for pipelining coherent operations2025
Input/output (I/O) store protocol for pipelining coherent operations2025
System for collaborative hardware RTL logic timing debug in integrated circuit d2025
Technique to handle insufficient on-chip memory capacity in decompressors2025
Decentralized hot cache line tracking fairness mechanism2024
Preemptive tracking of remote requests for decentralized hot cache line fairness2023
Handling an input/output store instruction2023
Directed interrupt virtualization with running indicator2023
Directed interrupt virtualization with running indicator2023
Method and processor system for executing a TELT instruction to access a data it2023
Heterogeneous services for enabling collaborative logic design and debug in aspe2023
Handling an input/output store instruction2023