Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory devices for multiple read operations

Memory devices for multiple read operations

US Patent 12142343 · Granted Nov 12, 2024

Estimated economic value: $38,266,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Program refresh with gate-induced drain leakage2025
Mitigating slow read disturb in a memory sub-system2025
Buffer allocation for reducing block transit penalty2025
Multiple-pass programming of memory cells using temporary parity generation2025
Temporary parity buffer allocation for zones in a parity group2025
Generating semi-soft bit data during corrective read operations in memory device2025
Generating semi-soft bit data during corrective read operations in memory device2025
Volatile data storage in NAND memory2025
Volatile data storage in NAND memory2025
Data age and validity-based memory management2025
Using a common pool of blocks for user data and a system data structure2025
Padding cached data with valid data for memory flush commands2025