Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Redundant through-silicon vias

Redundant through-silicon vias

US Patent 11705429 · Granted Jul 18, 2023

Estimated economic value: $8,312,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Repeater scheme for inter-die signals in multi-die package2025
Resistance welding electrodes, methods of welding flanges therewith, and vehicle2025
Inter-die signal load reduction technique in multi-die package2025
Pre-decoder circuitry2025
Methods for inspection of press-hardening steel surfaces prior to spot-welding f2025
Apparatus with calibration input mechanism and methods for operating the same2025
Asymmetric read-write sequence for interconnected dies2025
Divided quad clock-based inter-die clocking in a three-dimensional stacked memor2025
Divided clock transmission in a three-dimensional stacked memory device2024
Divided clock transmission in a three-dimensional stacked memory device2024
Separate inter-die connectors for data and error correction information and rela2024
Access command delay using delay locked loop (DLL) circuitry2024