Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Error avoidance in memory device

Error avoidance in memory device

US Patent 11704211 · Granted Jul 18, 2023

Estimated economic value: $248,707,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Feature-map throughput during training process2025
Accelerated memory copy operations2025
Configurable function approximation based on hardware selection of mapping table2025
Reducing power consumption in integrated circuits2025
Neural network processing based on subgraph recognition2025
Multi-threaded data movement request handling2025
Systolic array with input reduction to multiple reduced inputs2025
Crossbar based transpose data transfers2025
Crossbar based transpose data transfers2025
Arithmetic-intensity based load cloning2025
Flexible array data loading2025
Executing sublayers of a fully-connected layer2025