Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multi-phase topology synthesis of a network-on-chip (NoC)

Multi-phase topology synthesis of a network-on-chip (NoC)

US Patent 11657203 · Granted May 23, 2023

Estimated economic value: $3,498,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

System and method for deadlock detection in network-on-chip (NoC) having externa2025
System and method for deadlock detection in network-on-chip (NoC) having externa2025
System and method for transaction broadcast in a network on chip2025
System and method for performing transaction aggregation in a network-on-chip (N2025
Incremental topology modification of a network-on-chip2025
Incremental topology modification of a network-on-chip2025
System and method for synthesis of connectivity to an interconnect in a multi-pr2025
Topology synthesis of a network-on-chip (NoC)2025
System and method to generate a network-on-chip (NoC) description using incremen2025
System and method to generate a network-on-chip (NoC) description using incremen2025
System and method for editing a network-on-chip (NOC)2024
Constraints and objectives used in synthesis of a network-on-chip (NoC)2024