MC

Moez CHERIF

AR Arteris: 15 patents #1 of 48Top 3%
Overall (All Time): #304,452 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12348382 Incremental topology modification of a network-on-chip Benoit de LESCURE 2025-07-01
12237980 Topology synthesis of a network-on-chip (NoC) Benoit De LESCURE, Xavier Van Ruymbeke 2025-02-25
12204833 System and method to generate a network-on-chip (NoC) description using incremental topology synthesis Benoit de LESCURE 2025-01-21
12135928 Constraints and objectives used in synthesis of a network-on-chip (NoC) Benoit de LESCURE 2024-11-05
11956127 Incremental topology modification of a network-on-chip Benoit de LESCURE 2024-04-09
11836427 Constraints and objectives used in synthesis of a network-on-chip (NoC) Benoit de LESCURE 2023-12-05
11784909 Quality metrics for optimization tasks in generation of a network Benoit de LESCURE 2023-10-10
11748535 System and method to generate a network-on-chip (NoC) description using incremental topology synthesis Benoit de LESCURE 2023-09-05
11665776 System and method for synthesis of a network-on-chip for deadlock-free transformation Benoit de LESCURE 2023-05-30
11657203 Multi-phase topology synthesis of a network-on-chip (NoC) Benoit de LESCURE 2023-05-23
11601357 System and method for generation of quality metrics for optimization tasks in topology synthesis of a network Benoit de LESCURE 2023-03-07
11558259 System and method for generating and using physical roadmaps in network synthesis Benoit de LESCURE 2023-01-17
11449655 Synthesis of a network-on-chip (NoC) using performance constraints and objectives Benoit de LESCURE 2022-09-20
11121933 Physically aware topology synthesis of a network Benoit de LESCURE 2021-09-14
10990724 System and method for incremental topology synthesis of a network-on-chip Benoit de LESCURE 2021-04-27