Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references

Processor comprising a double multiplication and double addition operator actuable by an instruction with three operand references

US Patent 11604646 · Granted Mar 14, 2023

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Configurable inter-processor synchronization system2024
Processor with a configurable distribution of privileged resources and exception2024
Blockwise matrix multiplication system2021
Atomic instruction having a local scope limited to an intermediate cache level2021
Inter-processor synchronization system2021
Token bucket flow-rate limiter2019
VLIW type instruction packet structure and processor suitable for processing suc2019
Bit-matrix multiplication using explicit register2018
Hardware synchronization barrier between processing units2017
Stream management in an on-chip network2017
Mixed precision fused multiply-add operator2016
High-efficiency saturating operator2007