{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Plate node configurations and operations for a memory array", "item": "https://www.patentleaderboard.com/patent/11380696"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Plate node configurations and operations for a memory array

Plate node configurations and operations for a memory array

US Patent 11380696 · Granted Jul 5, 2022

Estimated economic value: $11,496,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory cell sensing architecture2025
Data masking for memory2025
Voltage management for improved tRP timing for FeRAM devices2025
Data invalidation for memory2025
Storing bits with cells in a memory device2025
PMOS threshold compensation sense amplifier for FeRAM devices2024
Memory array with multiplexed select lines and two transistor memory cells2024
Memory cell sensing using two step word line enabling2024
Sense amplifier with digit line multiplexing2024
Thin film transistor deck selection in a memory device2024
Data masking for memory2024
Charge-mirror based sensing for ferroelectric memory2024