Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces

Open-loop, super fast, half-rate clock and data recovery for next generation C-PHY interfaces

US Patent 11038666 · Granted Jun 15, 2021

Estimated economic value: $25,529,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Control signal generation for a delay line2025
Low-power synchronization using transition detection2025
Data communication apparatus with receiver employing transmitter supply voltage 2025
Data communication apparatus with receiver employing transmitter supply voltage 2025
Radio frequency interference common mode injection in a C-PHY receiver2025
Radio frequency interference common mode injection in a C-PHY receiver2025
Comparator integration time stabilization technique utilizing common mode mitiga2023
C-PHY receiver with self-regulated common mode servo loop2023
C-PHY receiver with self-regulated common mode servo loop2023
C-PHY receiver with self-regulated common mode servo loop2023
Device for measuring surface temperature of turbine blade based on rotatable pri2023
C-PHY half-rate wire state encoder and decoder2023