Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › NAND parity information techniques for systems with limited RAM

NAND parity information techniques for systems with limited RAM

US Patent 10977115 · Granted Apr 13, 2021

Estimated economic value: $23,307,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Program refresh with gate-induced drain leakage2025
Mitigating slow read disturb in a memory sub-system2025
Mitigating slow read disturb in a memory sub-system2025
Mitigating slow read disturb in a memory sub-system2025
Buffer allocation for reducing block transit penalty2025
Multi-stage erase operation of memory cells in a memory sub-system2025
Multiple-pass programming of memory cells using temporary parity generation2025
Processing write requests based on queue identifier2025
Temporary parity buffer allocation for zones in a parity group2025
Generating semi-soft bit data during corrective read operations in memory device2025
Preemptively warning host of background folding2025
Adaptive integrity scan rates in a memory sub-system based on block health metri2025