Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Hardware based state signature generation and check for test and debug of semiconductor circuit functionality

Hardware based state signature generation and check for test and debug of semiconductor circuit functionality

US Patent 10949591 · Granted Mar 16, 2021

Estimated economic value: $56,006,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Carry chain logic in processor based emulation system2020
Data array compaction in an emulation system2019
Method and system to mitigate large power load steps due to intermittent executi2019
Multiphase I/O for processor-based emulation system2018
Content addressable memory in an emulation system2017
Method and system for trace compaction during emulation of a circuit design2017
Compacting trace data generated by emulation processors during emulation of a ci2016
Method and system for modeling a flip-flop of a user design2016
Method and system for providing additional look-up tables2016
Method and system for dynamic selection of a memory read port2016
Hardware emulation method and system using a port time shift register2015
System and method implementing full-rate writes for simulation acceleration2015