Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Dual-layer dielectric in memory device

Dual-layer dielectric in memory device

US Patent 10629652 · Granted Apr 21, 2020

Estimated economic value: $45,742,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Active area salicidation for NMOS and PMOS devices2025
Integrated circuitry, array of cross-point memory cells, method used in forming 2025
Textured optoelectronic devices and associated methods of manufacture2025
Memory cells having increased structural stability2025
Vertical light emitting devices with nickel silicide bonding and methods of manu2024
Efficient fabrication of memory structures2024
Memory cells with asymmetrical electrode interfaces2024
Low resistance crosspoint architecture2024
Wafer overlay marks, overlay measurement systems, and related methods2023
Memory with optimized resistive layers2023
Textured optoelectronic devices and associated methods of manufacture2023
Methods for forming memory devices, and associated devices and systems2023