Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory hold margin characterization and correction circuit

Memory hold margin characterization and correction circuit

US Patent 10622044 · Granted Apr 14, 2020

Estimated economic value: $17,407,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

SRAM with burst mode operation2022
Systems and methods for providing a read only memory cell array2021
SRAM with burst mode operation2021
On-chip frequency monitoring2019
Intelligent bit line precharge for improved dynamic power2019
Dual sensing current latched sense amplifier2019
Metal layers for a three-port bit cell2018
Reducing leakage current in a memory device2018
Metal layers for a three-port bit cell2016
Intelligent bit line precharge for improved dynamic power2016
Word line and bit line tracking across diverse power domains2016
Reconfigurable memory interface circuit to support a built-in memory scan chain2015