Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory controller with error detection and retry modes of operation

Memory controller with error detection and retry modes of operation

US Patent 10621023 · Granted Apr 14, 2020

Estimated economic value: $2,608,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Memory controller partitioning for hybrid memory system2025
Semiconductor memory systems with on-die data buffering2025
DRAM interface mode with improved channel integrity and efficiency at high signa2025
MAC processing pipelines, circuitry to configure same, and methods of operating 2025
MAC processing pipeline having activation circuitry, and methods of operating sa2025
Dynamic random access memory (DRAM) component for high-performance, high-capacit2025
Dynamic random access memory (DRAM) component for high-performance, high-capacit2025
Energy-efficient error-correction-detection storage2025
Memory system with cached memory module operations2025
Configurable, power supply voltage referenced single-ended signaling with ESD pr2025
Memory system topologies including a memory die stack2025
Memory system with error detection2025