Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Simulating a single data rate (SDR) mode on a dual data rate (DDR) memory controller for calibrating DDR memory coarse alignment

Simulating a single data rate (SDR) mode on a dual data rate (DDR) memory controller for calibrating DDR memory coarse alignment

US Patent 10580476 · Granted Mar 3, 2020

Estimated economic value: $1,865,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Efficient and selective sparing of bits in memory systems2023
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory 2023
Packeted protocol device test system2022
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory 2021
Efficient and selective sparing of bits in memory systems2021
Hardware abstraction in software or firmware for hardware calibration2021
Efficient and selective sparing of bits in memory systems2020
Internally-generated data storage in spare memory locations2020
Memory device command-address-control calibration2020
Reference voltage calibration in memory during runtime2019
Per-DRAM and per-buffer addressability shadow registers and write-back functiona2019
Per-DRAM and per-buffer addressability shadow registers and write-back functiona2019