Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs

Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs

US Patent 10573714 · Granted Feb 25, 2020

Estimated economic value: $1,919,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Target qubit decoupling in an echoed cross-resonance gate2025
Calibration of two qubit gates involved in parallel operations2025
SRAM macro design architecture2025
Stacked SRAM cell architecture2025
Device structure for inducing layout dependent threshold voltage shift2025
Cable management assembly and cable management method2025
Nanosheet device with tri-layer bottom dielectric isolation2025
Detection system for suspension system of maglev train2024
Graphene/nanostructure FET with self-aligned contact and gate2024
Graphene/nanostructure FET with self-aligned contact and gate2024
Embedded microstrip transmission line2024
Pulsed stark tones for collision mitigation2024