Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Gain and memory error estimation in a pipeline analog to digital converter

Gain and memory error estimation in a pipeline analog to digital converter

US Patent 10541700 · Granted Jan 21, 2020

Estimated economic value: $25,062,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Analog-to-digital converter (ADC) having linearization circuit with reconfigurab2025
Analog-to-digital converter (ADC) having linearization circuit with reconfigurab2025
Analog-to-digital converter (ADC) having linearization circuit with reconfigurab2025
Analog-to-digital converter (ADC) having selective comparator offset error track2025
Metastability error detection and BER improvement technique in pipelined ADCs2025
Voltage-to-delay converter2025
Methods and apparatus to improve performance of voltage to delay converters2025
Calibration in non-linear multi-stage delay-to-digital conversion circuits2025
Multi-point reference distribution circuit2025
Methods and apparatus to convert analog voltages to delay signals2025
Balun with improved common mode rejection ratio2025
Noise-shaping of additive dither in analog-to-digital converters2025