{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Correcting power loss in NAND memory devices", "item": "https://www.patentleaderboard.com/patent/10430116"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Correcting power loss in NAND memory devices

Correcting power loss in NAND memory devices

US Patent 10430116 · Granted Oct 1, 2019

Estimated economic value: $10,821,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Trim setting determination on a memory device2025
Program refresh with gate-induced drain leakage2025
Mitigating slow read disturb in a memory sub-system2025
Buffer allocation for reducing block transit penalty2025
Buffer allocation for reducing block transit penalty2025
Multi-stage erase operation of memory cells in a memory sub-system2025
Multiple-pass programming of memory cells using temporary parity generation2025
Multiple-pass programming of memory cells using temporary parity generation2025
Processing write requests based on queue identifier2025
Temporary parity buffer allocation for zones in a parity group2025
Generating semi-soft bit data during corrective read operations in memory device2025
Preemptively warning host of background folding2025