Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Data lane validation procedure for multilane protocols

Data lane validation procedure for multilane protocols

US Patent 10402365 · Granted Sep 3, 2019

Estimated economic value: $18,086,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Asynchronous double data-lane DDR (ADL-DDR)2025
Asynchronous double data-lane DDR (ADL-DDR)2025
Time actuated triggers for a radio frequency front end2025
Bus interrupt debounce on a one-wire bidirectional bus2025
Bus interrupt debounce on a one-wire bidirectional bus2025
Automatic clock rate synchronization for 1-wire radio frequency front-end interf2025
Automatic clock rate synchronization for 1-wire radio frequency front-end interf2025
Mode switch for link-based and application-based security operations2025
Error handling for a mixed mode RFFE bus2025
Error handling for a mixed mode RFFE bus2025
Independent addressing of one-wire and two-wire devices on a shared RFFE bus int2024
Independent addressing of one-wire and two-wire devices on a shared RFFE bus int2024