Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

Performance-aware and reliability-aware data placement for n-level heterogeneous memory systems

US Patent 10365996 · Granted Jul 30, 2019

Estimated economic value: $35,149,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Enhanced page information co-processor2025
Adaptive address tracking2025
Access heatmap implementations at a host device2025
Delta predictions for page scheduling2025
Adaptive address tracking2025
Selective cache line memory encryption2025
Identifying matching virtual resources2025
Devices, systems, and methods for detecting and mitigating silent data corruptio2025
Handling permissions for virtualized file servers2025
Memory-aware pre-fetching and cache bypassing systems and methods2025
Devices, systems, and methods for out-of-band logging and delivery of error repo2025
Devices, systems, and methods for out-of-band delivery of error reports2025