{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Register allocation modes in a GPU based on total, maximum concurrent, and minimum number of registers needed by complex shaders", "item": "https://www.patentleaderboard.com/patent/10353859"}]}
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Home › Register allocation modes in a GPU based on total, maximum concurrent, and minimum number of registers needed by complex shaders

Register allocation modes in a GPU based on total, maximum concurrent, and minimum number of registers needed by complex shaders

US Patent 10353859 · Granted Jul 16, 2019

Estimated economic value: $38,969,000 ⓘ

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