Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Implementing DRAM refresh power optimization during long idle mode

Implementing DRAM refresh power optimization during long idle mode

US Patent 10304501 · Granted May 28, 2019

Estimated economic value: $2,255,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

MIPI C-PHY and D-PHY interface with shared driver, equalization, and data path c2025
Communications channel with multi-level signal transmission2024
Real-time error debugging2023
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory 2023
Method and apparatus to reduce bandwidth overhead of CRC protection on a memory 2021
Circuit-cycle reproduction2021
Instruction level tracing for analyzing processor failure2021
Thermally aware memory management2021
Thermally aware memory management2021
Core repair with failure analysis and recovery probe2021
Managing heterogeneous memory resource within a computing system2021
Managing heterogeneous memory resource within a computing system2021