{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Maintenance operations in a DRAM", "item": "https://www.patentleaderboard.com/patent/10248342"}]}
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Home › Maintenance operations in a DRAM

Maintenance operations in a DRAM

US Patent 10248342 · Granted Apr 2, 2019

Estimated economic value: $1,445,000 ⓘ

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