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Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-tip short or leakage, at least one side-to-side short or leakages, and at least one via respective tip-to-tip short, side-to-side short, and via open test areas

US Patent 10199285 · Granted Feb 5, 2019

Estimated economic value: $355,000

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