{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Apparatus configured to program memory cells using an intermediate level for multiple data states", "item": "https://www.patentleaderboard.com/patent/10147494"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Apparatus configured to program memory cells using an intermediate level for multiple data states

Apparatus configured to program memory cells using an intermediate level for multiple data states

US Patent 10147494 · Granted Dec 4, 2018

Estimated economic value: $13,328,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Self-optimizing corrective read offsets with lateral charge migration proxies2025
Program refresh with gate-induced drain leakage2025
Buffer allocation for reducing block transit penalty2025
Multiple-pass programming of memory cells using temporary parity generation2025
Temporary parity buffer allocation for zones in a parity group2025
Padding cached data with valid data for memory flush commands2025
Selectively programming retired wordlines of a memory device2025
Modified read counter incrementing scheme in a memory sub-system2025
Corrective reads with improved recovery from data retention loss2025
Memory devices with backside bond pads under a memory array2025
Sacrificial strings in a memory device to detect read disturb2025
Adaptive pre-read management in multi-pass programming2025