Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multiple liner interconnects for three dimensional memory devices and method of making thereof

Multiple liner interconnects for three dimensional memory devices and method of making thereof

US Patent 10115459 · Granted Oct 30, 2018

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Unselect word line switch bias scheme for non-volatile memory apparatus2025
Three-dimensional memory device including laterally separated source lines and m2025
Memory device including composite metal oxide semiconductor channels and methods2025
Memory device including composite metal oxide semiconductor channels and methods2025
Non-volatile memory with efficient testing2025
Bonded assembly including interconnect-level bonding pads and methods of forming2025
Bonded assembly including interconnect-level bonding pads and methods of forming2025
Three-dimensional nor array and method of making the same2025
Three-dimensional nor array and method of making the same2025
Three-dimensional nor array and method of making the same2025
Three-dimensional nor array and method of making the same2025
Three dimensional memory device containing resonant tunneling barrier and high m2025