Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment

Memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment

US Patent 10025536 · Granted Jul 17, 2018

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Nonvolatile memory with ongoing program read2025
Systems and methods to avoid over programming at infrequent smart verify acquisi2025
Mixed bitline lockout for QLC/TLC die2025
Three-bit-per-cell programming using a four-bit-per-cell programming algorithm2025
Command and address sequencing in parallel with data operations2025
Use of data latches for plane level compression of soft bit data in non-volatile2024
Non-volatile memory with shared data transfer latches2024
Architecture and data path options for compression of soft bit data in non-volat2024
On-the-fly compression scheme for soft bit data in non-volatile memory2024
Non-volatile storage system with program execution decoupled from dataload2024
Burst programming of a NAND flash cell2024
On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memo2024