Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8110495 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2012-02-07 |
| 7911060 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2011-03-22 |
| 7642654 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2010-01-05 |
| 7443031 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2008-10-28 |
| 7148572 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2006-12-12 |
| 6815338 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2004-11-09 |
| 6580176 | Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2003-06-17 |
| 6252427 | CMOS inverter and standard cell using the same | Tetsuya Ueda | 2001-06-26 |
| 6197685 | Method of producing multilayer wiring device with offset axises of upper and lower plugs | Hiroshi Masuda, Yoshiaki Kato, Kousaku Yano | 2001-03-06 |