WA

Wai Chung William Au

Oracle: 8 patents #1,503 of 14,854Top 15%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 San Jose, CA: #6,939 of 32,062 inventorsTop 25%
🗺 California: #66,801 of 386,348 inventorsTop 20%
Overall (All Time): #562,676 of 4,157,543Top 15%
9
Patents All Time

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDate
10599808 Method and system for determining circuit failure rate Govind Saraswat, Douglas Stanley, Anuj Trivedi 2020-03-24
10282507 Method and system for determining circuit failure rate Govind Saraswat, Douglas Stanley, Anuj Trivedi 2019-05-07
9836562 Iteratively simulating electrostatic discharges for a reduced netlist Qing He, Alexander Korobkov 2017-12-05
8645883 Integrated circuit simulation using fundamental and derivative circuit runs Alexander Korobkov, Subramanian Venkateswaran 2014-02-04
8341577 Parallel circuit simulation with partitions Alexander Korobkov, Subramanian Venkateswaran 2012-12-25
8024051 Parallel power grid analysis Alexander Korobkov 2011-09-20
7949970 Fast reduction of system models Alexander Korobkov 2011-05-24
7865348 Performance of circuit simulation with multiple combinations of input stimuli Alexander Korobkov 2011-01-04
7373289 Electrical isomorphism Bruce W. McGaughy, Baolin Yang 2008-05-13