Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9836562 | Iteratively simulating electrostatic discharges for a reduced netlist | Qing He, Wai Chung William Au | 2017-12-05 |
| 9275175 | Integrated circuit clock tree visualizer | Amit Agarwal | 2016-03-01 |
| 8645883 | Integrated circuit simulation using fundamental and derivative circuit runs | Wai Chung William Au, Subramanian Venkateswaran | 2014-02-04 |
| 8464195 | Integrated circuit clock analysis with macro models | Bogdan Tutuianu, Alexandre Ardelea, Amit Agarwal | 2013-06-11 |
| 8341577 | Parallel circuit simulation with partitions | Subramanian Venkateswaran, Wai Chung William Au | 2012-12-25 |
| 8190407 | Method and system for evaluating a device during circuit simulation | — | 2012-05-29 |
| 8024051 | Parallel power grid analysis | Wai Chung William Au | 2011-09-20 |
| 7953581 | System, method and apparatus for sensitivity based fast power grid simulation with variable time step | Michael Yu | 2011-05-31 |
| 7949970 | Fast reduction of system models | Wai Chung William Au | 2011-05-24 |
| 7865348 | Performance of circuit simulation with multiple combinations of input stimuli | Wai Chung William Au | 2011-01-04 |
| 7484195 | Method to improve time domain sensitivity analysis performance | — | 2009-01-27 |
| 7421671 | Graph pruning scheme for sensitivity analysis with partitions | — | 2008-09-02 |
| 7107200 | Method and apparatus for predicting clock skew for incomplete integrated circuit design | — | 2006-09-12 |
| 6912705 | Method and apparatus for performing operation on physical design data | — | 2005-06-28 |
| 6895524 | Circuit reduction technique for improving clock net analysis performance | — | 2005-05-17 |
| 6763509 | Method and apparatus for allocating decoupling capacitor cells | — | 2004-07-13 |