Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7565638 | Density-based layer filler for integrated circuit design | — | 2009-07-21 |
| 7404161 | Fullchip functional equivalency and physical verification | Arjun Dutt | 2008-07-22 |
| 7340710 | Integrated circuit binning and layout design system | Arjun Dutt | 2008-03-04 |
| 6941532 | Clock skew verification methodology for grid-based design | Manjunath D. Haritsa, Manishkumar B. Ankola, Ralf M. Schmitt, Anup K. Sharma, David M. Murata | 2005-09-06 |
| 6665845 | System and method for topology based noise estimation of submicron integrated circuit designs | Kathirqamar Aingaran, Manjunath D. Haritsa, Farn Wang | 2003-12-16 |