Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11526606 | Configuring machine learning model thresholds in models using imbalanced data sets | — | 2022-12-13 |
| 9569517 | Fault tolerant distributed key-value storage | Alexander Johannes Smola, Amr Ahmed, Eugene J. Shekita, Bor-Yiing Su | 2017-02-14 |
| 9230049 | Arraying power grid vias by tile cells | Timothy P. Johnson | 2016-01-05 |
| 8984449 | Dynamically generating jog patches for jog violations | — | 2015-03-17 |
| 8891878 | Method for representing images using quantized embeddings of scale-invariant image features | Shantanu Rane, Petros Boufounos | 2014-11-18 |
| 8719756 | Power grid mosaicing with deep-sub-tile cells | Timothy P. Johnson | 2014-05-06 |
| 8645453 | Method and system of processing cookies across domains | Limin Cheng, Qibu Luo | 2014-02-04 |
| 8423943 | Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow | — | 2013-04-16 |
| 8117581 | Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow | — | 2012-02-14 |
| 7519929 | Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules | — | 2009-04-14 |
| 7380227 | Automated correction of asymmetric enclosure rule violations in a design layout | — | 2008-05-27 |
| 7096447 | Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout | Suryanarayana R. Maturi, Pankaj Dixit | 2006-08-22 |
| 7007258 | Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout | — | 2006-02-28 |
| 6915252 | Method and system for ensuring consistency of design rule application in a CAD environment | — | 2005-07-05 |
| 6895568 | Correction of spacing violations between pure fill via areas in a multi-wide object class design layout | — | 2005-05-17 |
| 6892368 | Patching technique for correction of minimum area and jog design rule violations | Amy Yang | 2005-05-10 |
| 6892363 | Correction of width violations of dummy geometries | — | 2005-05-10 |
| 6883149 | Via enclosure rule check in a multi-wide object class design layout | Amy Yang | 2005-04-19 |
| 6871332 | Structure and method for separating geometries in a design layout into multi-wide object classes | Amy Yang | 2005-03-22 |
| 6832360 | Pure fill via area extraction in a multi-wide object class design layout | — | 2004-12-14 |
| 6816998 | Correction of spacing violations between dummy geometries and wide class objects of design geometries | — | 2004-11-09 |
| 6804808 | Redundant via rule check in a multi-wide object class design layout | Amy Yang | 2004-10-12 |
| 6792586 | Correction of spacing violations between wide class objects of dummy geometries | — | 2004-09-14 |
| 6775806 | Method, system and computer product to produce a computer-generated integrated circuit design | — | 2004-08-10 |
| 6772401 | Correction of spacing violations between design geometries and wide class objects of dummy geometries | — | 2004-08-03 |