Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11334109 | Variable-length clock stretcher with combiner timing logic | Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin | 2022-05-17 |
| 11323124 | Variable-length clock stretcher with correction for glitches due to finite DLL bandwidth | Fahim ur Rahman, Mahmood Khayatzadeh, Zuxu Qin | 2022-05-03 |
| 11290113 | Variable-length clock stretcher with correction for digital DLL glitches | Fahim ur Rahman, Sang Min Lee | 2022-03-29 |
| 11290114 | Variable-length clock stretcher with passive mode jitter reduction | Fahim ur Rahman, Mahmood Khayatzadeh | 2022-03-29 |
| 11239846 | Variable-length clock stretcher with correction for glitches due to phase detector offset | Fahim ur Rahman | 2022-02-01 |
| 10205375 | Automated power supply sense line selection | Georgios Konstadinidis, Changku Hwang | 2019-02-12 |
| 9602086 | Double half latch for clock gating | He Huang, Mayur Joshi, Ha Pham | 2017-03-21 |
| 9257972 | High speed dynamic flip-flop circuit with split output driver | Ha Pham, Hiep Ngo | 2016-02-09 |
| 8994429 | Energy efficient flip-flop with reduced setup time | Ha Pham | 2015-03-31 |
| 8860484 | Fine grain data-based clock gating | Ha Pham | 2014-10-14 |
| 8446791 | Process tolerant large-swing sense amplfier with latching capability | Ha Pham, Vaibhav Gupta | 2013-05-21 |
| 8324932 | High-speed static XOR circuit | Lancelot Kwong, Gaurav Shrivastav | 2012-12-04 |
| 7752410 | System and method for accessing data in a multicycle operations cache | Effendy Kumala | 2010-07-06 |
| 7084671 | Sense amplifier and method for making the same | Dennis L. Wendell, Howard Levy | 2006-08-01 |
| 6212117 | Duplicate bitline self-time technique for reliable memory operation | Kenichi Osada, Masood Ahmed Khan | 2001-04-03 |
| 6011719 | Digital signal processor having an on-chip pipelined EEPROM data memory and a on-chip pipelined EEPROM program memory | Karl L. Wang | 2000-01-04 |
| 5901086 | Pipelined fast-access floating gate memory architecture and method of operation | Karl L. Wang | 1999-05-04 |