Issued Patents All Time
Showing 101–110 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5923987 | Method for forming MOS devices with retrograde pocket regions and counter dopant regions at the substrate surface | — | 1999-07-13 |
| 5780912 | Asymmetric low power MOS devices | Michael P. Brassington | 1998-07-14 |
| 5773863 | Low power, high performance junction transistor | Michael P. Brassington | 1998-06-30 |
| 5753958 | Back-biasing in asymmetric MOS devices | Douglas A. Laird | 1998-05-19 |
| 5719422 | Low threshold voltage, high performance junction transistor | Michael P. Brassington | 1998-02-17 |
| 5650340 | Method of making asymmetric low power MOS devices | Michael P. Brassington | 1997-07-22 |
| 5640115 | Self-enabling latch | Sameer Halepete | 1997-06-17 |
| 5622880 | Method of making a low power, high performance junction transistor | Michael P. Brassington | 1997-04-22 |
| 5606270 | Dynamic clocked inverter latch with reduced charge leakage | Godfrey P. D'Souza, James Testa, Douglas A. Laird | 1997-02-25 |
| 4565966 | Method and apparatus for testing of electrical interconnection networks | Robert P. Burr, Raymond J. Keogh, Ronald Morino, Jonathan C. Crowell, James Christophersen | 1986-01-21 |