BD

Bulent Dervisoglu

OT On-Chip Technologies: 7 patents #2 of 3Top 70%
IN Intel: 4 patents #8,473 of 30,777Top 30%
CS Cadence Design Systems: 3 patents #541 of 2,263Top 25%
HP HP: 2 patents #2,312 of 7,018Top 35%
📍 Framingham, MA: #82 of 1,271 inventorsTop 7%
🗺 Massachusetts: #6,479 of 88,656 inventorsTop 8%
Overall (All Time): #257,325 of 4,157,543Top 7%
18
Patents All Time

Issued Patents All Time

Showing 1–18 of 18 patents

Patent #TitleCo-InventorsDate
8996938 On-chip service processor Laurence H. Cooke, Vacit Arat 2015-03-31
8239716 On-chip service processor Laurence H. Cooke, Vacit Arat 2012-08-07
7890899 Variable clocked scan test improvements Laurence H. Cooke 2011-02-15
7836371 On-chip service processor Laurence H. Cooke, Vacit Arat 2010-11-16
7752515 Accelerated scan circuitry and method for reducing scan test data volume and execution time Laurence H. Cooke 2010-07-06
7353470 Variable clocked scan test improvements Laurence H. Cooke 2008-04-01
7200784 Accelerated scan circuitry and method for reducing scan test data volume and execution time Laurence H. Cooke 2007-04-03
7197681 Accelerated scan circuitry and method for reducing scan test data volume and execution time Laurence H. Cooke 2007-03-27
7188286 Accelerated scan circuitry and method for reducing scan test data volume and execution time Laurence H. Cooke 2007-03-06
7181705 Hierarchical test circuit structure for chips with multiple circuit blocks Laurence H. Cooke 2007-02-20
7080301 On-chip service processor Laurence H. Cooke, Vacit Arat 2006-07-18
6964001 On-chip service processor Laurence H. Cooke, Vacit Arat 2005-11-08
6886121 Hierarchical test circuit structure for chips with multiple circuit blocks Laurence H. Cooke 2005-04-26
6687865 On-chip service processor for test and debug of integrated circuits Laurence H. Cooke, Vacit Arat 2004-02-03
6631504 Hierarchical test circuit structure for chips with multiple circuit blocks Laurence H. Cooke 2003-10-07
6594802 Method and apparatus for providing optimized access to circuits for debug, programming, and test Michael Ricchetti, Christopher J. Clark 2003-07-15
5257223 Flip-flop circuit with controllable copying between slave and scan latches — 1993-10-26
5068881 Scannable register with delay test capability Gayvin Stong 1991-11-26