Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10635845 | Method and apparatus for improving Boolean satisfiability solver generated based on input design with data qualifier signals | Yael Meller, Or Davidi | 2020-04-28 |
| 10599802 | Methods for automatic engineering change order (ECO) bug fixing in integrated circuit design | Or Davidi | 2020-03-24 |
| 10460060 | Checking equivalence between changes made in a circuit definition language and changes in post-synthesis nets | Or Davidi | 2019-10-29 |
| 10140405 | Method and apparatus for finding logic equivalence between register transfer level and post synthesis nets | Or Davidi | 2018-11-27 |
| 9390208 | Formal verification of temporal properties expressed using local variables | Dana Fisman Ofek, Naiyong Jin | 2016-07-12 |
| 8700606 | Methods for calculating a combined impact analysis repository | Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss | 2014-04-15 |
| 8321407 | Methods for calculating a combined impact analysis repository | Yossi Cohen, Mati Cohen, Nurit Dor, Dror Weiss | 2012-11-27 |