Issued Patents All Time
Showing 26–46 of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9519538 | Error recovery following speculative execution with an instruction processing pipeline | Shidhartha Das, David Michael Bull | 2016-12-13 |
| 9269418 | Apparatus and method for controlling refreshing of data in a DRAM | Donald Felton, Sachin Satish Idgunji | 2016-02-23 |
| 9116844 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus | Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles | 2015-08-25 |
| 9032188 | Issue policy control within a multi-threaded in-order superscalar processor | Stuart David Biles | 2015-05-12 |
| 9021298 | Integrated circuit with error repair and fault tolerance | Shidhartha Das, David Michael Bull | 2015-04-28 |
| 8862935 | Integrated circuit with error repair and fault tolerance | Shidhartha Das, David Michael Bull | 2014-10-14 |
| 8826097 | Memory scrubbing | Sachin Satish Idgunji | 2014-09-02 |
| 8732523 | Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus | Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles | 2014-05-20 |
| 8694862 | Data processing apparatus using implicit data storage data storage and method of implicit data storage | Yiannakis Sazeides, Daniel Kershaw, Jean-Baptiste Brelot | 2014-04-08 |
| 8621272 | Integrated circuit with error repair and fault tolerance | Shidhartha Das, David Michael Bull | 2013-12-31 |
| 8327118 | Scheduling control within a data processing system | David Michael Bull, Shidhartha Das | 2012-12-04 |
| 8205206 | Data processing apparatus and method for managing multiple program threads executed by processing circuitry | Stuart David Biles | 2012-06-19 |
| 8195886 | Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit | Stuart David Biles | 2012-06-05 |
| 8099556 | Cache miss detection in a data processing apparatus | Mrinmoy Ghosh, Stuart David Biles | 2012-01-17 |
| 8037287 | Error recovery following speculative execution with an instruction processing pipeline | Shidhartha Das, David Michael Bull | 2011-10-11 |
| 7979642 | Managing the storage of high-priority storage items in storage units in multi-core and multi-threaded systems using history storage and control circuitry | David Michael Bull | 2011-07-12 |
| 7937535 | Managing cache coherency in a data processing apparatus | Stuart David Biles, Simon Andrew Ford | 2011-05-03 |
| 7895469 | Integrated circuit using speculative execution | David Michael Bull, Shidhartha Das | 2011-02-22 |
| 7805595 | Data processing apparatus and method for updating prediction data based on an operation's priority level | Alastair David Reid, Stuart David Biles | 2010-09-28 |
| 7769955 | Multiple thread instruction fetch from different cache levels | Stuart David Biles | 2010-08-03 |
| 7707390 | Instruction issue control within a multi-threaded in-order superscalar processor | Vladimir Vasekin, Stuart David Biles | 2010-04-27 |