Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7545671 | Static random access memory cell with improved stability | Stephen V. Kosonocky, Sampath Purushothaman, Kenneth P. Rodbell | 2009-06-09 |
| 7397691 | Static random access memory cell with improved stability | Stephen V. Kosonocky, Sampath Purushothaman, Kenneth P. Rodbell | 2008-07-08 |
| 7259986 | Circuits and methods for providing low voltage, high performance register files | Stephen V. Kosonocky | 2007-08-21 |
| 7180818 | High performance register file with bootstrapped storage supply and method of reading data therefrom | Rajiv V. Joshi | 2007-02-20 |
| 6977519 | Digital logic with reduced leakage | Suhwan Kim, Daniel R. Knebel, Stephen V. Kosonocky | 2005-12-20 |
| 6975532 | Quasi-static random access memory | Stephen V. Kosonocky | 2005-12-13 |
| 6920061 | Loadless NMOS four transistor dynamic dual Vt SRAM cell | Rajiv V. Joshi, Stephen V. Kosonocky | 2005-07-19 |
| 6876595 | Decode path gated low active power SRAM | Stephen V. Kosonocky | 2005-04-05 |
| 6861739 | Minimum metal consumption power distribution network on a bonded die | Ashok K. Kapoor | 2005-03-01 |
| 6839299 | Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells | Stephen V. Kosonocky | 2005-01-04 |
| 6791886 | SRAM cell with bootstrapped power line | Stephen V. Kosonocky, Rajiv V. Joshi | 2004-09-14 |
| 6788566 | Self-timed read and write assist and restore circuit | Stephen V. Kosonocky, Rajiv V. Joshi | 2004-09-07 |
| 6683805 | Suppression of leakage currents in VLSI logic and memory circuits | Rajiv V. Joshi, Louis L. Hsu | 2004-01-27 |
| 6529400 | Source pulsed, dynamic threshold complementary metal oxide semiconductor static RAM cells | Ashok K. Kapoor | 2003-03-04 |
| 6515893 | Source pulsed, low voltage CMOS SRAM cell for fast, stable operation | — | 2003-02-04 |