Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Akiyoshi Asai — 11 Patents

NCNippondenso Co.: 7 patents #296 of 3,479Top 9%
Denso: 4 patents #3,129 of 11,792Top 30%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Akiyoshi Asai has been granted 11 US patents while listed as an inventor at Nippondenso Co.. The first was granted in 1994 and the most recent in June 2018. Akiyoshi Asai ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Akiyoshi Asai in Kariya, MH, JP.

Patents per Year

Patents granted per year, 1994 to 2018Bar chart with a peak of 3 patents in 1998.peak 31994: 1 patents19941996: 1 patents19961997: 2 patents19971998: 3 patents19981999: 1 patents19992000: 1 patents20002001: 1 patents20012018: 1 patents2018

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
10002841 Semiconductor device Shotaro Miyawaki, Naohiko Hirano, Yasutomi Asai 2018-06-19
6191007 Method for manufacturing a semiconductor substrate Masaki Matsui, Shoichi Yamauchi, Hisayoshi Ohshima, Kunihiro Onoda, Takanari Sasaya +2 more 2001-02-20
6150697 Semiconductor apparatus having high withstand voltage Akihiko Teshigahara, Kunihiro Onoda, Hiroyasu Itou, Ryuichirou Abe, Toshio Sakakibara 2000-11-21
5869872 Semiconductor integrated circuit device and manufacturing method for the same Jun Sakakibara, Megumi Suzuki, Seiji Fujino 1999-02-09
5786616 Semiconductor integrated circuit having an SOI structure, provided with a protective circuit Harutsugu Fukumoto, Hiroaki Tanaka 1998-07-28
5751041 Semiconductor integrated circuit device Megumi Suzuki, Jun Sakakibara 1998-05-12
5736770 Semiconductor device with conductive connecting layer and abutting insulator section made of oxide of same material Nobuyuki Ohya, Mitsutaka Katada 1998-04-07
5663588 Semiconductor device having an SOI structure of mesa isolation type and manufacturing method therefor Megumi Suzuki, Kazuhiro Tsuruta 1997-09-02
5610426 Semiconductor integrated circuit device having excellent dual polarity overvoltage protection characteristics Kazuhiro Tsuruta, Takeshi Enya 1997-03-11
5488243 SOI MOSFET with floating gate Kazuhiro Tsuruta, Hiroaki Himi, Seiji Fujino 1996-01-30
5279981 Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell Shigemitsu Fukatsu 1994-01-18