Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10002841 | Semiconductor device | Shotaro Miyawaki, Naohiko Hirano, Yasutomi Asai | 2018-06-19 |
| 6191007 | Method for manufacturing a semiconductor substrate | Masaki Matsui, Shoichi Yamauchi, Hisayoshi Ohshima, Kunihiro Onoda, Takanari Sasaya +2 more | 2001-02-20 |
| 6150697 | Semiconductor apparatus having high withstand voltage | Akihiko Teshigahara, Kunihiro Onoda, Hiroyasu Itou, Ryuichirou Abe, Toshio Sakakibara | 2000-11-21 |
| 5869872 | Semiconductor integrated circuit device and manufacturing method for the same | Jun Sakakibara, Megumi Suzuki, Seiji Fujino | 1999-02-09 |
| 5786616 | Semiconductor integrated circuit having an SOI structure, provided with a protective circuit | Harutsugu Fukumoto, Hiroaki Tanaka | 1998-07-28 |
| 5751041 | Semiconductor integrated circuit device | Megumi Suzuki, Jun Sakakibara | 1998-05-12 |
| 5736770 | Semiconductor device with conductive connecting layer and abutting insulator section made of oxide of same material | Nobuyuki Ohya, Mitsutaka Katada | 1998-04-07 |
| 5663588 | Semiconductor device having an SOI structure of mesa isolation type and manufacturing method therefor | Megumi Suzuki, Kazuhiro Tsuruta | 1997-09-02 |
| 5610426 | Semiconductor integrated circuit device having excellent dual polarity overvoltage protection characteristics | Kazuhiro Tsuruta, Takeshi Enya | 1997-03-11 |
| 5488243 | SOI MOSFET with floating gate | Kazuhiro Tsuruta, Hiroaki Himi, Seiji Fujino | 1996-01-30 |
| 5279981 | Method of reducing the trap density of an oxide film for application to fabricating a nonvolatile memory cell | Shigemitsu Fukatsu | 1994-01-18 |