Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10664370 | Multiple core analysis mode for defect analysis | Kenji Shiozawa, Yoshihide Nakamura, Takuya LEE, Yutaka Nakadai, Hiroyuki Sasaki | 2020-05-26 |
| 10656201 | Semiconductor device | Takuya LEE, Yutaka Nakadai, Kenji Shiozawa, Yoshihide Nakamura | 2020-05-19 |
| 7376931 | Method for providing layout design and photo mask | — | 2008-05-20 |
| 6413808 | Semiconductor device and process for production thereof | — | 2002-07-02 |
| 6124613 | SOI-MOS field effect transistor that withdraws excess carrier through a carrier path silicon layer | — | 2000-09-26 |
| 6008716 | Fuse structure connecting first level and second level interconnections in inter-layer insulator | — | 1999-12-28 |
| 5712492 | Transistor for checking radiation-hardened transistor | — | 1998-01-27 |
| 5675171 | Integrated insulated gate field effect transistors with thin insulation region between field insulation regions | — | 1997-10-07 |
| 5498894 | Semiconductor device | — | 1996-03-12 |